1. Field of the Invention
This invention is related to the field of bus interfaces, and more particularly, to retry mechanisms in bus interfaces.
2. Description of the Related Art
Generally, devices in a system may use a bus to communicate. Particularly, it is frequent that a variety of peripheral devices are coupled to a bus (e.g. the Peripheral Component Interconnect bus, or PCI bus) for communicating with other devices (either directly connected to the bus or indirectly through one or more bus bridges). The bus is a shared resource among the devices coupled to the bus, and thus efficient use of the bandwidth available on the bus may be important to overall system performance. During the time that a transaction is active on the bus, other transactions may be precluded from being initiated or completing. For example, the PCI bus is a shared address/data bus in which the address and data are transferred on the same lines (but at different times). A transaction initiated on the PCI bus consumes bus bandwidth until the data is transferred or until the transaction is retried. Other buses may implement separate address and data buses, but even these buses may have wasted bandwidth. For example, if the data bus is granted to a transaction, the transaction consumes data bus bandwidth until the data is actually transferred.
In order to enforce efficient bandwidth usage, some buses (such as the PCI bus) may specify a maximum latency that a target device may delay before performing at least the first data transfer of a read transaction. If the target device cannot transfer data within the maximum latency, then the target device must retry the transaction (thus freeing the bus for use to perform another transaction). In the time between the retry and the subsequent reattempt of the transaction by the initiating device, the target device may continue to make progress toward being able to transfer data. For example, for a read transaction, the target device may continue to fetch the requested data internally.
Many PCI bus devices currently implement a static counter which counts to a timeout value (e.g. the maximum specified latency or some predetermined latency less than the maximum latency) and, if the timeout is reached without data available for transfer, the PCI device retries the transaction. Other PCI devices (particularly long latency devices) may implement a policy of always retrying a read transaction the first time the read transaction is presented on the PCI bus, and initiating an internal read to begin fetching the requested data. Still further, other devices may implement each of the above policies, selectable as modes for the device under software control.
Unfortunately, the aforementioned mechanisms tend to be wasteful of PCI bus bandwidth. A more efficient retry mechanism is therefore desired.